1. Field of the Invention
The present invention relates to D/A converters which convert digital signals into analog signals and are used for signal processing in the field of audio equipment and the like. In particular, it relates to a switched capacitor D/A converter capable of operating at a low supply voltage and outputting analog signals low inharmonic components and noise components, and to a delta-sigma D/A converter using thereof.
2. Description of the Prior Art
In an audio area, a so-called delta-sigma D/A converter, for example, such as the one shown in FIG. 6 has been proposed as a signal converter which converts high-bit (16-bit) digital input signals used, for example, in compact disks (CDs) into analog output signals. The signal converter 10 interpolates high-bit (16-bit) digital input signals 64 to 128 times using a digital filter 11. Then, a digital delta-sigma modulator 12 converts the interpolated digital signals into lower-bit (lower-resolution) digital signals. Then, a signal control circuit 13 converts the digital signals into digital data suitable for controlling a switched capacitor D/A converter 15 in the next stage, and the switched capacitor D/A converter 15 produces analog output signals.
Regarding the switched capacitor D/A converter 15, various types have been proposed. For example, a switched capacitor D/A converter 40 described in Japanese Patent Laid-Open No. 11-055121 applied by this applicant comprises an operational amplifier 100 whose output terminal and inverting input terminal are connected by a capacitive element Cfb and whose non-inverting input terminal is connected to an analog ground, as shown in FIG. 7. Also, it comprises capacitive elements C1 to Ci; a switch SB connected between the capacitive elements C1 to Ci and the inverting input terminal of the operational amplifier 100; switches SU1 to SUi which connect the right terminals of the respective capacitive elements C1 to Ci, i.e., the terminals connected with the switch SB, to the analog ground; switches SUG1 to SUGi which connect the left terminals of the capacitive elements C1 to Ci with one of reference voltages (Vr+ and Vrxe2x88x92); switches SY1 to SYi connected between the left terminals of the respective capacitive elements C1 to Ci and the output terminal of the operational amplifier 100; and a clock supplier 200 which supplies two types of clock xcfx861 and xcfx862.
The capacitive elements C1 to Ci hold charges which correspond to a predetermined reference voltage based on digital data during a first period and the capacitive elements C1 to Ci are connected between the inverting input terminal and output terminal of the operational amplifier 100 during a second period.
Specifically, when the clock xcfx861 is in high state, the capacitive element Cx is operated according to the polarity of digital data Sx (x=1 to i). For example, if the digital data Sx is xe2x80x9c1,xe2x80x9d the capacitive element Cx is connected between the reference voltage Vr+ and analog ground and positive charges are sampled onto the capacitive element Cx. If the digital data Sx is xe2x80x9cxe2x88x921,xe2x80x9d the capacitive element Cx is connected between the reference voltage Vrxe2x88x92 and digital ground and negative charges are sampled. When the clock xcfx862 is in high state, the capacitive element Cx is connected between the output terminal and inverting input terminal of the operational amplifier 100.
When the switched capacitor D/A converter 40 shown in FIG. 7 is implemented as a MOS integrated circuit and operated at a positive power supply potential VDD and a negative power supply potential 0 [V], a high reference voltage is used and so-called kT/C noise attributable to sampling by capacitive elements is reduced to maximize S/N ratio. Besides, to simplify configuration, the reference voltage Vr+ is set at VDD, the reference voltage Vrxe2x88x92 is set at 0 [V], and the analog ground is set at the midpoint potential (xc2xd)xc2x7VDD of the supply voltage.
FIG. 8 shows potentials of various parts around the capacitive element Ci. In FIG. 8A, where the reference voltage Vr+ is selected, the switch SUGi which connects the capacitive element Ci with one of the reference voltages (Vr+ and Vrxe2x88x92) corresponds to a MOS switch Q1 consisting of a MOS transistor while the switch SUi which connects the capacitive element Ci to the analog ground corresponds to a MOS switch Q2. In FIG. 8B, where the reference voltage Vrxe2x88x92 is selected, the switch SUi corresponds to a MOS switch Q3 while the switch SUGi corresponds to a MOS switch Q4.
If the MOS switches Q2 and Q3 connected to the analog ground consist of n-channel MOS transistors as shown in FIGS. 8A and 8B, the source potential is (xc2xd)xc2x7VDD. If the gate potential is VDD, the gate-source potential VGS of the MOS switches Q2 and Q3 is (xc2xd)xc2x7VDD.
However, if the MOS integrated circuit is operated at a low supply voltage, since the switches (Q2 and Q3, in this case) connected to the analog ground consist of MOS transistors, the MOS switches may not turn on and charges may not be able to be sampled onto the capacitive elements during the first period depending on relationship between the gate-source voltage VGS and a threshold voltage VT of the MOS transistors.
FIG. 9 shows correspondence between source potential and resistance (so-called ON resistance) when n-channel MOS transistors of the same size conduct at different supply voltages. In FIG. 9, the horizontal axis represents the source potential while the vertical axis represents the ON resistance. A characteristic line L1 has the lowest supply voltage VDD and the rightmost characteristic line has the highest supply voltage VDD. The ON resistances of the characteristic lines L1 to L3 at the source voltage of (xc2xd)xc2x7VDD are indicated by ◯ marks.
As shown in FIG. 9, the ON resistance at the source voltage of (xc2xd)xc2x7VDD rises sharply as the supply voltage VDD lowers. Thus, in order to sample charges within a predetermined period of time, the size of the MOS transistors must be increased to lower the ON resistance.
However, increasing the size of the MOS transistors which compose switches will increase the feed-through noise produced when the gate voltage changes during sampling of charges and the switches are turned off. This will cause variations in the amount of charge among samplings, making the operational amplifier 100 produce harmonics and/or noise.
Even if changes in the threshold voltage VT due to a substrate effect are ignored, if the gate-source voltage, i.e., (xc2xd)xc2x7VDD, is not higher than the threshold voltage VT, MOS switches do not turn on, and thus the minimum operating supply voltage VDD is VDD=2xc2x7VT.
Similarly, if the switches connected to the analog ground consist of p-channel MOS transistors, since the MOS switches Q2 and Q3 in FIG. 8A are p-channel MOS transistors, the gate-source voltage VGS is (xc2xd)xc2x7VDD as with the above case. Thus, if (xc2xd)xc2x7VDD is not higher than the threshold voltage VT, the MOS switches Q2 and Q3 do not turn on, and thus the minimum operating supply voltage VDD is VDD=2xc2x7VT. Incidentally, the threshold voltage VT of p-channel MOS transistors is negative, and its absolute value is used here.
If the MOS switches Q2 and Q3 connected to the analog ground consist of an n-channel MOS transistor and p-channel MOS transistor connected in parallel, the gate-source voltage VGS of the MOS transistors is also (xc2xd)xc2x7VDD. Thus, if the gate-source voltage VGS lowers below the lower of the threshold voltages VT of the two MOS transistors which compose the MOS switches, MOS switches do not turn on, so the minimum operating supply voltage VDD is determined based on the lower of the threshold voltages VT. In short, the minimum operating supply voltage VDD is restricted by the threshold voltages VT of the MOS switches.
Thus, the object of the present invention is to provide D/A converters which can operate at a low supply voltage and can give good output.
The present invention provides a D/A converter for converting a given digital signal into an analog signal, comprising: a first capacitive element for holding a charge corresponding to difference between a charge-holding supply voltage and a first reference voltage based on the given digital signal during a first period; a second capacitive element for holding a charge corresponding to difference between the charge-holding supply voltage and a second reference voltage different from the first reference voltage based on the given digital signal during the first period; and switching means which connects the first and second capacitive elements between an input terminal and output terminal of an operational amplifier during a second period.
With this configuration, during the first period, the first capacitive element holds the charge corresponding to the difference between the charge-holding supply voltage and first reference voltage while the second capacitive element holds the charge corresponding to the difference between the charge-holding supply voltage and second reference voltage based on the given digital signal, and then during the second period, the first and second capacitive elements are connected between the input terminal and output terminal of the operational amplifier. This makes it possible to implement a D/A converter which can operate at a lower supply voltage and produce output signals low in harmonic components and noise components.
Furthermore, for a fully differential configuration, the D/A converter may further comprise a third capacitive element for holding a charge corresponding to the difference between the charge-holding supply voltage and the first reference voltage during the first period and a fourth capacitive element for holding a charge corresponding to the difference between the charge-holding supply voltage and the second reference voltage during the first period. In that case, a second switch is needed to connect the third and fourth capacitive elements between a non-inverting input terminal and inverting output terminal of the operational amplifier.
The switching means are especially effective in reducing voltage if they comprise MOS transistors.
Preferably, the first reference voltage is a supply voltage and the second reference voltage is a ground voltage because this eliminates the need to generate an intermediate voltage.
The D/A converter described above can be used for a delta-sigma D/A converter which converts a digital signal sampled at a predetermined sampling frequency into an analog signal.
Specifically, the delta-sigma D/A converter comprises a digital filter which converts the digital signal into a second digital signal with a higher frequency than a sampling frequency by interpolating it; a digital delta-sigma modulator which converts the second digital signal into a lower-bit third digital signal using noise shaping; and a D/A converter which performs digital-analog conversion, wherein this D/A converter may be the D/A converter described above. The delta-sigma D/A converter may also be fully differential.